tr****@wi****.com & 480444****

Travis M. Williams (active Clearance)

480.444.6683 | [email protected] | [email protected] 15+ years in Software / Firmware design and development for defense applications. 8+... | Phoenix, Phoenix, United States

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Travis M. Williams (active Clearance)’s Emails tr****@wi****.com

Travis M. Williams (active Clearance)’s Phone Numbers 480444****

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Travis M. Williams (active Clearance)’s Location Phoenix, Phoenix, United States

Travis M. Williams (active Clearance)’s Expertise 480.444.6683 | [email protected] | [email protected] 15+ years in Software / Firmware design and development for defense applications. 8+ years in Booking Management Internet Business sales revenue 200k annually. 2+ years Aerospace Engineering supporting DO-254 requirement verification. Employee Full Medical Benefits UHC (PPO) EXTENDED TECHNICAL QUALIFICATIONS: - Bachelor of Science in Electrical Engineering (BSEE) - Completed nine(9) credit hours towards Master of Science in Electrical Engineering (MSEE) - Cyber Security Graduate Certificate (Stanford University) - 15 years of FPGA Design Experience Xilinx: Spartan 3, Virtex 2 - 7 Series, Kintex Ultrascale, Altera Cyclone III, Stratix and Lattice - VHDL and System Verilog coding for synthesis, simulation, programming, debugging, and behavior modeling - Experience with Digital Simulation: RTL & Gate Level - Experience with Digital Systems Engineering Design and Modeling - Experience with boundary scan (BIST), JTAG, Chipscope, ILA, IBERT, VIO, MIG cores - Experience with Avionics design and familiarity of industry standards: DO-254, DO-181C, DO-185A, DO-185B, DO-218B - Experience integrating secure data cores such as: AES, DES - Experience designing Simulink FIR and IIR filters - Experience with PCI, PCI Express - Experience with Memory Devices: DDR3, DDR3, QDR II+ SRAM - Experience with Software design and C/C++ language, UNIX/LINUX shell scripting, tcl scripting, - Experience with Protocol Interfaces: DS101, DS102, RS422, RS232, AIM ASIC KMCE, SERDES, I2C, LVDS, SPI SOFTWARE: VHDL, System Verilog, C, Python, TCL, LINUX, DOORS, Quartus, Synplify, Xilinx Vivado, EDK, ModelSim, Chipscope, Xemacs, virSim, NCSim, Rational Suite, SVN HARDWARE: Annapolis DSP Boards, Spectrum Signal Processing [COTS] Pro-3500, ePMC-FPGA8120, VME, Labview RIO, Curtiss Wright CHAMP FX4 / CAML-MOD3 Camera Link module CLEARANCES: 2012 Last Active DOD Secret, SBI/ESBI, SCI w. Counter Intelligence (CI) Polygraph

Travis M. Williams (active Clearance)’s Current Industry Northrop Grumman

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Work Experience

Northrop Grumman

Senior FPGA Designer (Aerotek W2)

Wed Jul 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Cobham Aviation Services

Senior FPGA Designer (Bentley Resources Global Resources x WilliamsConsultant Team) C2C

Wed May 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)

Collins Aerospace

ASIC Designer (Bentley Resources Global Resources x WilliamsConsultant Team) C2C

Wed Aug 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)

General Dynamics Mission Systems

Senior Systems Engineer (EXB Solutions x Williams Consultant Team) C2C

Mon Jan 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)

Curtiss-Wright Defense Solutions

Senior FPGA Designer (Carlton National Contractor W2)

Mon May 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Oct 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

Lockheed Martin

SYSTEM VERILOG / FPGA FIRMWARE(FW) DESIGNER ( DCR Contractor W2 )

Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Apr 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

UTC Aerospace Systems

SENIOR FPGA FIRMWARE(FW) DESIGNER (Aerotek Contractor W2 )

Wed Jul 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Parker Hannifin Corporation

SENIOR FPGA FIRMWARE(FW) DESIGNER - Embraer MLJ/MSJ (CDI CONTRACTOR W2 )

Mon Jul 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Northrop Grumman Corporation

SENIOR FPGA DESIGNER - APR - 39 (AEROTEK CONTRACTOR W2 )

Fri Mar 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

Honeywel Space

SR. LEAD ENGINEER / FPGA Designer - R&D - (EXPERIS CONTRACTOR W2)

Sat Oct 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

Languages

Travis M. Williams (active Clearance) Email Addresses

tr****@wi****.com Work Email

tr****@wi****.com Personal Email

tr****@st****.edu Personal Email

Travis M. Williams (active Clearance) Phone Number

480444**** Phone number

FAQ About Travis M. Williams (active Clearance)

Travis M. Williams (active Clearance) is located at
Phoenix, Phoenix, United States

Travis M. Williams (active Clearance) is a
480.444.6683 | [email protected] | [email protected] 15+ years in Software / Firmware design and development for defense applications. 8+ years in Booking Management Internet Business sales revenue 200k annually. 2+ years Aerospace Engineering supporting DO-254 requirement verification. Employee Full Medical Benefits UHC (PPO) EXTENDED TECHNICAL QUALIFICATIONS: - Bachelor of Science in Electrical Engineering (BSEE) - Completed nine(9) credit hours towards Master of Science in Electrical Engineering (MSEE) - Cyber Security Graduate Certificate (Stanford University) - 15 years of FPGA Design Experience Xilinx: Spartan 3, Virtex 2 - 7 Series, Kintex Ultrascale, Altera Cyclone III, Stratix and Lattice - VHDL and System Verilog coding for synthesis, simulation, programming, debugging, and behavior modeling - Experience with Digital Simulation: RTL & Gate Level - Experience with Digital Systems Engineering Design and Modeling - Experience with boundary scan (BIST), JTAG, Chipscope, ILA, IBERT, VIO, MIG cores - Experience with Avionics design and familiarity of industry standards: DO-254, DO-181C, DO-185A, DO-185B, DO-218B - Experience integrating secure data cores such as: AES, DES - Experience designing Simulink FIR and IIR filters - Experience with PCI, PCI Express - Experience with Memory Devices: DDR3, DDR3, QDR II+ SRAM - Experience with Software design and C/C++ language, UNIX/LINUX shell scripting, tcl scripting, - Experience with Protocol Interfaces: DS101, DS102, RS422, RS232, AIM ASIC KMCE, SERDES, I2C, LVDS, SPI SOFTWARE: VHDL, System Verilog, C, Python, TCL, LINUX, DOORS, Quartus, Synplify, Xilinx Vivado, EDK, ModelSim, Chipscope, Xemacs, virSim, NCSim, Rational Suite, SVN HARDWARE: Annapolis DSP Boards, Spectrum Signal Processing [COTS] Pro-3500, ePMC-FPGA8120, VME, Labview RIO, Curtiss Wright CHAMP FX4 / CAML-MOD3 Camera Link module CLEARANCES: 2012 Last Active DOD Secret, SBI/ESBI, SCI w. Counter Intelligence (CI) Polygraph Northrop Grumman

Travis M. Williams (active Clearance) currently works in the
Northrop Grumman

Travis M. Williams (active Clearance) specializes in
480.444.6683 | [email protected] | [email protected] 15+ years in Software / Firmware design and development for defense applications. 8+ years in Booking Management Internet Business sales revenue 200k annually. 2+ years Aerospace Engineering supporting DO-254 requirement verification. Employee Full Medical Benefits UHC (PPO) EXTENDED TECHNICAL QUALIFICATIONS: - Bachelor of Science in Electrical Engineering (BSEE) - Completed nine(9) credit hours towards Master of Science in Electrical Engineering (MSEE) - Cyber Security Graduate Certificate (Stanford University) - 15 years of FPGA Design Experience Xilinx: Spartan 3, Virtex 2 - 7 Series, Kintex Ultrascale, Altera Cyclone III, Stratix and Lattice - VHDL and System Verilog coding for synthesis, simulation, programming, debugging, and behavior modeling - Experience with Digital Simulation: RTL & Gate Level - Experience with Digital Systems Engineering Design and Modeling - Experience with boundary scan (BIST), JTAG, Chipscope, ILA, IBERT, VIO, MIG cores - Experience with Avionics design and familiarity of industry standards: DO-254, DO-181C, DO-185A, DO-185B, DO-218B - Experience integrating secure data cores such as: AES, DES - Experience designing Simulink FIR and IIR filters - Experience with PCI, PCI Express - Experience with Memory Devices: DDR3, DDR3, QDR II+ SRAM - Experience with Software design and C/C++ language, UNIX/LINUX shell scripting, tcl scripting, - Experience with Protocol Interfaces: DS101, DS102, RS422, RS232, AIM ASIC KMCE, SERDES, I2C, LVDS, SPI SOFTWARE: VHDL, System Verilog, C, Python, TCL, LINUX, DOORS, Quartus, Synplify, Xilinx Vivado, EDK, ModelSim, Chipscope, Xemacs, virSim, NCSim, Rational Suite, SVN HARDWARE: Annapolis DSP Boards, Spectrum Signal Processing [COTS] Pro-3500, ePMC-FPGA8120, VME, Labview RIO, Curtiss Wright CHAMP FX4 / CAML-MOD3 Camera Link module CLEARANCES: 2012 Last Active DOD Secret, SBI/ESBI, SCI w. Counter Intelligence (CI) Polygraph

Travis M. Williams (active Clearance) speaks the following languages:
No languages available.

Travis M. Williams (active Clearance) has prior experience in the following industries:
Northrop Grumman , Cobham Aviation Services , Collins Aerospace , General Dynamics Mission Systems , Curtiss-Wright Defense Solutions , Lockheed Martin , UTC Aerospace Systems , Parker Hannifin Corporation , Northrop Grumman Corporation , Honeywel Space

Travis M. Williams (active Clearance) has the following professional experience:
Northrop Grumman , Cobham Aviation Services , Collins Aerospace , General Dynamics Mission Systems , Curtiss-Wright Defense Solutions , Lockheed Martin , UTC Aerospace Systems , Parker Hannifin Corporation , Northrop Grumman Corporation , Honeywel Space .